Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains. In fact, it addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques. An RTL or gate-level simulation of a design (that has multiple clock domains) does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process. The 0-In CDC verification solution rectifies this problem. The 0-In CDC verification solution sets the industry benchmark by providing the three essential elements for a...
Mentor Graphics Design for Test v8 2009.1 Linux 确保设计能于制造后正确工作 DFT工具为设计的可测性增加了设计电路（RTL或者gate level） DFT工具为投入生产的设计生成测试组来检测其缺陷 基于DFT结果进行失效分析 product:Mentor Graphics Design for Test v8 2009.1 Linux Lanaguage:English Platform:/Linux Size:278MB
Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. \”For our mobile phone chip design, we needed a solution that could address peak current problems...
FineSim Pro defines a new paradigm in full-chip circuit-level simulation, enabling the simulation of the most challenging analog/mixed-signal SoCs with SPICE accuracy and unprecedented performance. Diagram * Combination of accuracy and performance in a single executable allows large, mixed-signal designs to be simulated with very accurate SPICE and fast-SPICE solving techniques. This provides complete control of speed- versus-accuracy tradeoffs throughout the entire design. * Multi-CPU simulation enabled through Magma’s Native Parallel Technology TM delivers silicon-accurate results for very large complex systems (5M transistors and more) such as wireless systems on chip (SoCs) and full-chip memory designs. * Electrically Exact Models TM (E2M) dramatically improve simulation performance by orders of magnitude with virtually no loss in accuracy compared to fast SPICE....
In the exploration and production (E&P) field, state-of-the-art 3D modeling and construction of 3D grids is roughly equivalent among competing applications: the conventional technique for constructing a model is pillar-based. Unfortunately, in environments containing Y faults or oblique faults, this pillar-based construction requires modifications of the faults geometry and/or removal from the model. The technique introduces deformations of the grid cell geometry which adversely affect distribution of petrophysical properties and flow simulation results. A Step-Change in ModelingSKUA, the Subsurface Knowledge Unified Approach, is a 3D methodology that unifies all subsurface discrete models. SKUA embeds a native, fully-3D description of the faulted volumes. This is achieved by using the UVT Transform™, a technology based on the observation that horizons represent geochronologic...
Paradigm Interpret 2008 well test analysis software is an invaluable tool for performing pressure transient analysis from a wide variety of data sources. It can be used in the design and analysis of pressure transients from traditional production tests, drillstem tests (DST), wireline formation tests (WFT) and testing-while-drilling on exploration, appraisal or production wells. Interpret combines powerful modeling capabilities with an intuitive user interface. Running under Microsoft® Windows®, it is fully interoperable with Microsoft Office. Interpret 2008 builds upon the strengths of previous releases with many new features and enhancements. These include new options for performing deconvolution on the pressure history prior to diagnosing the appropriate model and for fitting gradients for multi-session WFT analysis. Powerful and intuitive diagnostics enable the...
GOLDEN, COLORADO – Golden Software Inc. has upgraded its Surfer contouring and 3D mapping package with the ability to apply transparency to solid colors, map layers, fill patterns, and images. Users have full control over the opacity percentage. Surfer also boasts the ability to import and export georeferenced image files. Users can create fully rendered 3D surfaces and overlay aerial photography, satellite imagery and other images on these 3D surfaces with real world coordinates. Apply transparency to the overlaid imagery to create photo-realistic 3D models containing both terrain and ground cover detail. Surfer 9, with more than 100 new features and enhancements, is now available at a retail price of $599. Upgrades from previous Surfer versions are only $199. Purchase...
VMG Sim 2.8软件特色 Product:vmgsim 2.8 Lanaguage:English Platform:/win2000/winxp Size:80MB
With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers can account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. It combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. It also offers the latest capabilities to support advanced 65nm and 45nm designs. Features/Benefits * Supports multiple implementation styles with built-in power-planning, floorplanning, and signal integrity analysis * Supports multiple methodologies for flip-chip implementation, promoting concurrent chip/package design * Provides a statistical static timing analysis solution and standardized ECSM library models * Incorporates cutting-edge yield and low-power design capabilities * Handles 50M+ gate designs at 90nm and below Encounter...
LMS SCADAS Mobile, power and flexibility for lab and field testing LMS SCADAS Mobile, power and flexibility for lab and field testingLMS Test.Xpress is seamlessly integrated with the state-of-the- art LMS SCADAS Mobile front-ends. The LMS SCADAS Mobile is one of the most powerful, compact and lightweight data acquisition front-ends of its class: up to 102,4 kHz sampling rate per channel, 24 bits resolution, 105 dB signal to noise ratio, 2.2 Msamples/s throughput rate – all bundled into a fully rugged and ultra portable front-end package.You can chose the ultra-portable 4 to 8 channel SCM01 system or go for the laptop-sizeproduct:LMS Test Xpress V3A SL1 Lanaguage:english Platform:Winxp/Win7 Size:590MB